Regviz

stm32 /stm32h7 /STM32H755_CM7 /DSIHOST /DSI_CLTCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_CLTCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7/STM32H745_CM4/DSIHOST/DSI_CLTCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LP2HS_TIME0HS2LP_TIME

Description

DSI Host clock lane timer configuration register

Fields

LP2HS_TIME

LP2HS_TIME
HS2LP_TIME

HS2LP_TIME

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32