Regviz

stm32 /stm32h7 /STM32H755_CM7 /DSIHOST /DSI_ISR0

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Interpret as DSI_ISR0

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https://regviz.com/r/stm32/stm32h7/STM32H745_CM4/DSIHOST/DSI_ISR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AE0)AE0 0 (AE1)AE1 0 (AE2)AE2 0 (AE3)AE3 0 (AE4)AE4 0 (AE5)AE5 0 (AE6)AE6 0 (AE7)AE7 0 (AE8)AE8 0 (AE9)AE9 0 (AE10)AE10 0 (AE11)AE11 0 (AE12)AE12 0 (AE13)AE13 0 (AE14)AE14 0 (AE15)AE15 0 (PE0)PE0 0 (PE1)PE1 0 (PE2)PE2 0 (PE3)PE3 0 (PE4)PE4

Description

DSI Host interrupt and status register 0

Fields

AE0

AE0
AE1

AE1
AE2

AE2
AE3

AE3
AE4

AE4
AE5

AE5
AE6

AE6
AE7

AE7
AE8

AE8
AE9

AE9
AE10

AE10
AE11

AE11
AE12

AE12
AE13

AE13
AE14

AE14
AE15

AE15
PE0

PE0
PE1

PE1
PE2

PE2
PE3

PE3
PE4

PE4

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32