DSI wrapper PHY configuration register 0
| UIX4 | UIX4 |
| SWCL | SWCL |
| SWDL0 | SWDL0 |
| SWDL1 | SWDL1 |
| HSICL | HSICL |
| HSIDL0 | HSIDL0 |
| HSIDL1 | HSIDL1 |
| FTXSMCL | FTXSMCL |
| FTXSMDL | FTXSMDL |
| CDOFFDL | CDOFFDL |
| TDDL | TDDL |
| PDEN | Pull-down enable |
| TCLKPREPEN | Custom time for tCLK-PREPARE enable |
| TCLKZEROEN | Custom time for tCLK-ZERO enable |
| THSPREPEN | Custom time for tHS-PREPARE enable |
| THSTRAILEN | Custom time for tHS-TRAIL enable |
| THSZEROEN | Custom time for tHS-ZERO enable |
| TLPXDEN | Custom time for tLPX for data lanes enable |
| THSEXITEN | Custom time for tHS-EXIT enable |
| TLPXCEN | Custom time for tLPX for clock lane enable |
| TCLKPOSTEN | Custom time for tCLK-POST enable |