This register is used to control the concerned channel.
| EN | channel enable |
| TEIE | Transfer error interrupt enable This bit is set and cleared by software. |
| CTCIE | Channel Transfer Complete interrupt enable This bit is set and cleared by software. |
| BRTIE | Block Repeat transfer interrupt enable This bit is set and cleared by software. |
| BTIE | Block Transfer interrupt enable This bit is set and cleared by software. |
| TCIE | buffer Transfer Complete interrupt enable This bit is set and cleared by software. |
| PL | Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. |
| BEX | byte Endianness exchange |
| HEX | Half word Endianes exchange |
| WEX | Word Endianness exchange |
| SWRQ | SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access). |