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stm32 /stm32h7 /STM32H755_CM7 /SYSCFG /CCCSR

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Interpret as CCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (CS)CS 0 (READY)READY 0 (HSLV)HSLV

Description

compensation cell control/status register

Fields

EN

enable
CS

Code selection
READY

Compensation cell ready flag
HSLV

High-speed at low-voltage

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32