Regviz

stm32 /stm32h7 /STM32H757_CM4 /OTG1_HS_GLOBAL /OTG_HS_GRSTCTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OTG_HS_GRSTCTL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f7/STM32F722/OTG_HS_GLOBAL/OTG_HS_GRSTCTL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSRST)CSRST 0 (HSRST)HSRST 0 (FCRST)FCRST 0 (RXFFLSH)RXFFLSH 0 (TXFFLSH)TXFFLSH 0TXFNUM0 (DMAREQ)DMAREQ 0 (AHBIDL)AHBIDL

Description

OTG_HS reset register

Fields

CSRST

Core soft reset
HSRST

HCLK soft reset
FCRST

Host frame counter reset
RXFFLSH

RxFIFO flush
TXFFLSH

TxFIFO flush
TXFNUM

TxFIFO number
DMAREQ

DMA request signal enabled for USB OTG HS
AHBIDL

AHB master idle

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32