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stm32 /stm32h7 /STM32H757_CM7 /BDMA /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GIF1)GIF1 0 (TCIF1)TCIF1 0 (HTIF1)HTIF1 0 (TEIF1)TEIF1 0 (GIF2)GIF2 0 (TCIF2)TCIF2 0 (HTIF2)HTIF2 0 (TEIF2)TEIF2 0 (GIF3)GIF3 0 (TCIF3)TCIF3 0 (HTIF3)HTIF3 0 (TEIF3)TEIF3 0 (GIF4)GIF4 0 (TCIF4)TCIF4 0 (HTIF4)HTIF4 0 (TEIF4)TEIF4 0 (GIF5)GIF5 0 (TCIF5)TCIF5 0 (HTIF5)HTIF5 0 (TEIF5)TEIF5 0 (GIF6)GIF6 0 (TCIF6)TCIF6 0 (HTIF6)HTIF6 0 (TEIF6)TEIF6 0 (GIF7)GIF7 0 (TCIF7)TCIF7 0 (HTIF7)HTIF7 0 (TEIF7)TEIF7 0 (GIF8)GIF8 0 (TCIF8)TCIF8 0 (HTIF8)HTIF8 0 (TEIF8)TEIF8

Description

DMA interrupt status register

Fields

GIF1

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF1

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF1

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF1

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF2

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF2

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF2

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF2

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF3

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF3

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF3

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF3

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF4

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF4

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF4

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF4

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF5

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF5

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF5

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF5

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF6

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF6

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF6

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF6

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF7

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF7

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF7

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF7

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
GIF8

Channel x global interrupt flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TCIF8

Channel x transfer complete flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
HTIF8

Channel x half transfer flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
TEIF8

Channel x transfer error flag (x = 1…8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32