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stm32 /stm32h7 /STM32H757_CM7 /MDMA /MDMA_C8ISR

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Interpret as MDMA_C8ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF8)TEIF8 0 (CTCIF8)CTCIF8 0 (BRTIF8)BRTIF8 0 (BTIF8)BTIF8 0 (TCIF8)TCIF8 0 (CRQA8)CRQA8

Description

MDMA channel x interrupt/status register

Fields

TEIF8

Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
CTCIF8

Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
BRTIF8

Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
BTIF8

Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
TCIF8

channel x buffer transfer complete
CRQA8

channel x request active flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32