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stm32 /stm32h7 /STM32H7A3 /ADC2 /DIFSEL

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Interpret as DIFSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIFSEL

Description

ADC channel differential or single-ended mode selection register

Fields

DIFSEL

ADC channel differential or single-ended mode for channel

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32