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stm32 /stm32h7 /STM32H7A3 /HRTIM_Common /DISR

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Interpret as DISR

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https://regviz.com/r/stm32/stm32h7/STM32H742/HRTIM_Common/DISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TA1ODIS)TA1ODIS 0 (TA2ODIS)TA2ODIS 0 (TB1ODIS)TB1ODIS 0 (TB2ODIS)TB2ODIS 0 (TC1ODIS)TC1ODIS 0 (TC2ODIS)TC2ODIS 0 (TD1ODIS)TD1ODIS 0 (TD2ODIS)TD2ODIS 0 (TE1ODIS)TE1ODIS 0 (TE2ODIS)TE2ODIS

Description

DISR

Fields

TA1ODIS

TA1ODIS
TA2ODIS

TA2ODIS
TB1ODIS

TB1ODIS
TB2ODIS

TB2ODIS
TC1ODIS

TC1ODIS
TC2ODIS

TC2ODIS
TD1ODIS

TD1ODIS
TD2ODIS

TD2ODIS
TE1ODIS

TE1ODIS
TE2ODIS

TE2ODIS

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32