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stm32 /stm32h7 /STM32H7A3 /HRTIM_Master /MISR

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Interpret as MISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MCMP1)MCMP1 0 (MCMP2)MCMP2 0 (MCMP3)MCMP3 0 (MCMP4)MCMP4 0 (MREP)MREP 0 (SYNC)SYNC 0 (MUPD)MUPD

Description

Master Timer Interrupt Status Register

Fields

MCMP1

Master Compare 1 Interrupt Flag
MCMP2

Master Compare 2 Interrupt Flag
MCMP3

Master Compare 3 Interrupt Flag
MCMP4

Master Compare 4 Interrupt Flag
MREP

Master Repetition Interrupt Flag
SYNC

Sync Input Interrupt Flag
MUPD

Master Update Interrupt Flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32