Regviz

stm32 /stm32h7 /STM32H7A3 /JPEG /CONFR0

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Interpret as CONFR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START

Description

JPEG codec control register

Fields

START

Start This bit start or stop the encoding or decoding process. Read this register always return 0.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32