Regviz

stm32 /stm32h7 /STM32H7A3 /OTG1_HS_PWRCLK /OTG_HS_PCGCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OTG_HS_PCGCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f2/STM32F215/OTG_HS_PWRCLK/OTG_HS_PCGCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STPPCLK)STPPCLK 0 (GATEHCLK)GATEHCLK 0 (PHYSUSP)PHYSUSP

Description

Power and clock gating control register

Fields

STPPCLK

Stop PHY clock
GATEHCLK

Gate HCLK
PHYSUSP

PHY suspended

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32