Regviz

stm32 /stm32h7 /STM32H7A3 /SPI1 /UDRDR

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Interpret as UDRDR

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31282724232019161512118743000000000000000000000000000000000000000000UDRDR

Description

Underrun Data Register

Fields

UDRDR

Data at slave underrun condition

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32