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stm32 /stm32h7 /STM32H7B0 /DBGMCU /APB4FZ1

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Interpret as APB4FZ1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (I2C4)I2C4 0 (LPTIM2)LPTIM2 0 (LPTIM3)LPTIM3 0 (RTC)RTC 0 (WDGLSCD)WDGLSCD

Description

DBGMCU APB4 peripheral freeze register

Fields

I2C4

I2C4 SMBUS timeout stop in debug
LPTIM2

LPTIM2 stop in debug
LPTIM3

LPTIM3 stop in debug
RTC

RTC stop in debug
WDGLSCD

LS watchdog for CPU domain stop in debug

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32