stm32 /stm32h7 /STM32H7B0 /Flash /FLASH_CR2

Bank 2 configuration lock bit This bit locks the FLASH_CR2 register. The correct write sequence to FLASH_KEYR2 register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_KEYR2 is performed twice, this bit remains locked until next system reset. LOCK2 can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK2 changes from 0 to 1, the other bits of FLASH_CR2 register do not change.

0 (B_0x0): FLASH_CR2 register unlocked

1 (B_0x1): FLASH_CR2 register locked

Bank 2 internal buffer control bit Setting PG2 bit to 1 enables internal buffer for write operations to bank 2. This allows the preparation of program operations even if a sector or bank erase is ongoing. PG2 can be programmed only when LOCK2 is cleared to 0. When PG2 is reset, the internal buffer is disabled for write operations to bank 2 and all the data stored in the buffer but not sent to the operation queue are lost.

Bank 2 sector erase request Setting SER2 bit to 1 requests a sector erase on bank 2. SER2 can be programmed only when LOCK2 is cleared to 0. BER2 has a higher priority than SER2: if both are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a sector erase is required on protected sector(s).

0 (B_0x0): sector erase not requested on bank 2

1 (B_0x1): sector erase requested on bank 2

Bank 2 erase request Setting BER2 bit to 1 requests a bank erase operation on bank 2 (user Flash memory only). BER2 can be programmed only when LOCK2 is cleared to 0. BER2 has a higher priority than SER2: if both are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a bank erase is required and some sectors are protected.

0 (B_0x0): bank erase not requested on bank 2

1 (B_0x1): bank erase requested on bank 2

Bank 2 write forcing control bit FW2 forces a write operation even if the write buffer is not full. FW2 can be programmed only when LOCK2 is cleared to 0. The embedded Flash memory resets FW2 when the corresponding operation has been acknowledged. Write forcing is effective only if the write buffer is not empty. In particular, FW2 does not start several write operations when the write operations are performed consecutively.

Bank 2 erase start control bit START2 bit is used to start a sector erase or a bank erase operation. START2 can be programmed only when LOCK2 is cleared to 0. The embedded Flash memory resets START2 when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged.

Bank 2 sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SSN2 can be programmed only when LOCK2 is cleared to 0. … … Note: Bank 2 is limited to 64 sectors on STM32H7A3xG devices.

0 (B_0x0): Sector 0 of user Flash bank 2 selected

1 (B_0x1): Sector 1of user Flash bank 2 selected

63 (B_0x3F): Sector 63 of user Flash bank 2 selected

127 (B_0x7F): Sector 127 of user Flash bank 2 selected

Bank 2 CRC control bit Setting CRC_EN bit to 1 enables the CRC calculation on bank 2. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR2 register. When CRC calculation is performed on bank 2, it can only be disabled by setting CRC_EN bit to 0. Resetting CRC_EN clears CRC configuration and resets the content of FLASH_CRCDATAR register. CRC_EN can be programmed only when LOCK2 is cleared to 0.

Bank 2 end-of-program interrupt control bit Setting EOPIE2 bit to 1 enables the generation of an interrupt at the end of a program operation to bank 2. EOPIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated at the end of a program operation to bank 2.

1 (B_0x1): interrupt enabled when at the end of a program operation to bank 2.

Bank 2 write protection error interrupt enable bit When WRPERRIE2 bit is set to 1, an interrupt is generated when a protection error occurs during a program operation to bank 2. WRPERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a protection error occurs on bank 2

1 (B_0x1): interrupt generated when a protection error occurs on bank 2.

Bank 2 programming sequence error interrupt enable bit When PGSERRIE2 bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation to bank 2. PGSERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a sequence error occurs on bank 2

1 (B_0x1): interrupt generated when sequence error occurs on bank 2.

Bank 2 strobe error interrupt enable bit When STRBERRIE2 bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 2. STRBERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a strobe error occurs on bank 2

1 (B_0x1): interrupt generated when strobe error occurs on bank 2.

Bank 2 inconsistency error interrupt enable bit When INCERRIE2 bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation to bank 2. INCERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a inconsistency error occurs on bank 2

1 (B_0x1): interrupt generated when a inconsistency error occurs on bank 2.

Bank 2 read protection error interrupt enable bit When RDPERRIE2 bit is set to 1, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP or by RDP level 1) during a read operation from bank 2. RDPERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a read protection error occurs on bank 2

1 (B_0x1): an interrupt is generated when a read protection error occurs on bank 2

Bank 2 secure error interrupt enable bit When RDSERRIE2 bit is set to 1, an interrupt is generated when a secure error (access to a secure-only protected address) occurs during a read operation from bank 2. RDSERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a secure error occurs on bank 2

1 (B_0x1): an interrupt is generated when a secure error occurs on bank 2

Bank 2 ECC single correction error interrupt enable bit When SNECCERRIE2 bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 2. SNECCERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when an ECC single correction error occurs on bank 2

1 (B_0x1): interrupt generated when an ECC single correction error occurs on bank 2

Bank 2 ECC double detection error interrupt enable bit When DBECCERRIE2 bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 2. DBECCERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when an ECC double detection error occurs on bank 2

1 (B_0x1): interrupt generated if an ECC double detection error occurs on bank 2

Bank 2 CRC end of calculation interrupt enable bit When CRCENDIE2 bit is set to 1, an interrupt is generated when the CRC computation has completed on bank 2. CRCENDIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when CRC computation complete on bank 2

1 (B_0x1): interrupt generated when CRC computation complete on bank 2

Bank 2 CRC read error interrupt enable bit When CRCRDERRIE2 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 2. CRCRDERRIE2 can be programmed only when LOCK2 is cleared to 0.

0 (B_0x0): no interrupt generated when a CRC read error occurs on bank 2

1 (B_0x1): interrupt generated when a CRC read error occurs on bank 2