stm32 /stm32h7 /STM32H7B0 /Flash /FLASH_SR2

Bank 2 busy flag BSY2 flag is set when an effective write or erase operation is ongoing to bank 2. It is not possible to know what type of operation is being executed. BSY2 cannot be forced to 0. It is automatically reset by hardware every time a step in a write, or erase operation completes.

0 (B_0x0): no write or erase operation is executed on bank 2

1 (B_0x1): a write or an erase operation is being executed on bank 2.

Bank 2 write buffer not empty flag WBNE2 flag is set when embedded Flash memory is waiting for new data to complete the write buffer. In this state the write buffer is not empty. WBNE2 is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW2 bit in FLASH_CR2 the embedded Flash memory detects an error that involves data loss the application software has disabled write operations in this bank This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions or send the missing data.

0 (B_0x0): write buffer of bank 2 empty or full

1 (B_0x1): write buffer of bank 2 waiting data to complete

Bank 2 wait queue flag QW2 flag is set when a write or erase operation is pending in the command queue buffer of bank 2. It is not possible to know what type of operation is present in the queue. This flag is reset by hardware when all write/erase operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested.

0 (B_0x0): no write or erase operation is waiting in the operation queues of bank 2

1 (B_0x1): at least one write or erase operation is pending in the operation queues of bank 2

Bank 2 CRC busy flag CRC_BUSY2 flag is set when a CRC calculation is ongoing on bank 2. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation on bank 2.

0 (B_0x0): no CRC calculation ongoing on bank 2

1 (B_0x1): CRC calculation ongoing on bank 2.

Bank 2 end-of-program flag EOP2 flag is set when a programming operation to bank 2 completes. An interrupt is generated if the EOPIE2 is set to 1. It is not necessary to reset EOP2 before starting a new operation. EOP2 bit is cleared by writing 1 to CLR_EOP2 bit in FLASH_CCR2 register.

0 (B_0x0): no programming operation completed on bank 2

1 (B_0x1): a programming operation completed on bank 2

Bank 2 write protection error flag WRPERR2 flag is raised when a protection error occurs during a program operation to bank 2. An interrupt is also generated if the WRPERRIE2 is set to 1. Writing 1 to CLR_WRPERR2 bit in FLASH_CCR2 register clears WRPERR2.

0 (B_0x0): no write protection error occurred on bank 2

1 (B_0x1): a write protection error occurred on bank 2

Bank 2 programming sequence error flag PGSERR2 flag is raised when a sequence error occurs on bank 2. An interrupt is generated if the PGSERRIE2 bit is set to 1. Writing 1 to CLR_PGSERR2 bit in FLASH_CCR2 register clears PGSERR2.

0 (B_0x0): no sequence error occurred on bank 2

1 (B_0x1): a sequence error occurred on bank 2.

Bank 2 strobe error flag STRBERR2 flag is raised when a strobe error occurs on bank 2 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE2 bit is set to 1. Writing 1 to CLR_STRBERR2 bit in FLASH_CCR2 register clears STRBERR2.

0 (B_0x0): no strobe error occurred on bank 2

1 (B_0x1): a strobe error occurred on bank 2.

Bank 2 inconsistency error flag INCERR2 flag is raised when a inconsistency error occurs on bank 2. An interrupt is generated if INCERRIE2 is set to 1. Writing 1 to CLR_INCERR2 bit in the FLASH_CCR2 register clears INCERR2.

0 (B_0x0): no inconsistency error occurred on bank 2

1 (B_0x1): an inconsistency error occurred on bank 2.

Bank 2 read protection error flag RDPERR2 flag is raised when a read protection error (read access to a PCROP-protected word or a RDP-protected area) occurs on bank 2. An interrupt is generated if RDPERRIE2 is set to 1. Writing 1 to CLR_RDPERR2 bit in FLASH_CCR2 register clears RDPERR2.

0 (B_0x0): no read protection error occurs on bank 2

1 (B_0x1): a read protection error occurs on bank 2

Bank 2 secure error flag RDSERR2 flag is raised when a read secure error (read access to a secure-only protected word) occurs on bank 2. An interrupt is generated if RDSERRIE2 is set to 1. Writing 1 to CLR_RDSERR2 bit in FLASH_CCR2 register clears RDSERR2.

0 (B_0x0): no secure error occurs on bank 2

1 (B_0x1): a secure error occurs on bank 2

Bank 2 single correction error flag SNECCERR2 flag is raised when an ECC single correction error occurs during a read operation from bank 2. An interrupt is generated if SNECCERRIE2 is set to 1. Writing 1 to CLR_SNECCERR2 bit in FLASH_CCR2 register clears SNECCERR2.

0 (B_0x0): no ECC single correction error occurs on bank 2

1 (B_0x1): ECC single correction error occurs on bank 2

Bank 2 ECC double detection error flag DBECCERR2 flag is raised when an ECC double detection error occurs during a read operation from bank 2. An interrupt is generated if DBECCERRIE2 is set to 1. Writing 1 to CLR_DBECCERR2 bit in FLASH_CCR2 register clears DBECCERR2.

0 (B_0x0): no ECC double detection error occurs on bank 2

1 (B_0x1): ECC double detection error occurs on bank 2

Bank 2 CRC end of calculation flag CRCEND2 bit is raised when the CRC computation has completed on bank 2. An interrupt is generated if CRCENDIE2 is set to 1. It is not necessary to reset CRCEND2 before restarting CRC computation. Writing 1 to CLR_CRCEND2 bit in FLASH_CCR2 register clears CRCEND2.

0 (B_0x0): CRC computation not complete on bank 2

1 (B_0x1): CRC computation complete on bank 2

Bank 2 CRC read error flag CRCRDERR2 flag is raised when a word is found read protected during a CRC operation on bank 2. An interrupt is generated if CRCRDIE2 and CRCEND2 are set to 1. Writing 1 to CLR_CRCRDERR2 bit in FLASH_CCR2 register clears CRCRDERR2. Note: This flag is valid only when CRCEND2 bit is set to 1.

0 (B_0x0): no protected area inside the address read by CRC on bank 2

1 (B_0x1): a protected area inside the address read by CRC on bank 2. CRC result is very likely incorrect.