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stm32 /stm32h7 /STM32H7B0 /HRTIM_Common /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MUDIS)MUDIS 0 (TAUDIS)TAUDIS 0 (TBUDIS)TBUDIS 0 (TCUDIS)TCUDIS 0 (TDUDIS)TDUDIS 0 (TEUDIS)TEUDIS 0AD1USRC 0AD2USRC 0AD3USRC 0AD4USRC

Description

Control Register 1

Fields

MUDIS

Master Update Disable
TAUDIS

Timer A Update Disable
TBUDIS

Timer B Update Disable
TCUDIS

Timer C Update Disable
TDUDIS

Timer D Update Disable
TEUDIS

Timer E Update Disable
AD1USRC

ADC Trigger 1 Update Source
AD2USRC

ADC Trigger 2 Update Source
AD3USRC

ADC Trigger 3 Update Source
AD4USRC

ADC Trigger 4 Update Source

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32