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stm32 /stm32h7 /STM32H7B0 /HRTIM_Common /OENR

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Interpret as OENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TA1OEN)TA1OEN 0 (TA2OEN)TA2OEN 0 (TB1OEN)TB1OEN 0 (TB2OEN)TB2OEN 0 (TC1OEN)TC1OEN 0 (TC2OEN)TC2OEN 0 (TD1OEN)TD1OEN 0 (TD2OEN)TD2OEN 0 (TE1OEN)TE1OEN 0 (TE2OEN)TE2OEN

Description

Output Enable Register

Fields

TA1OEN

Timer A Output 1 Enable
TA2OEN

Timer A Output 2 Enable
TB1OEN

Timer B Output 1 Enable
TB2OEN

Timer B Output 2 Enable
TC1OEN

Timer C Output 1 Enable
TC2OEN

Timer C Output 2 Enable
TD1OEN

Timer D Output 1 Enable
TD2OEN

Timer D Output 2 Enable
TE1OEN

Timer E Output 1 Enable
TE2OEN

Timer E Output 2 Enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32