SDMMC1EN=B_0x0, OCTOSPI1EN=B_0x0, DMA2DEN=B_0x0, OCTOSPIMEN=B_0x0, MDMAEN=B_0x0, GFXMMUEN=B_0x0, OTFD2EN=B_0x0, OCTOSPI2EN=B_0x0, OTFD1EN=B_0x0, JPGDECEN=B_0x0, FMCEN=B_0x0
| MDMAEN | MDMA peripheral clock enable Set and reset by software. 0 (B_0x0): MDMA peripheral clock disabled (default after reset) 1 (B_0x1): MDMA peripheral clock enabled |
| DMA2DEN | DMA2D peripheral clock enable Set and reset by software. 0 (B_0x0): DMA2D peripheral clock disabled (default after reset) 1 (B_0x1): DMA2D peripheral clock enabled |
| JPGDECEN | JPGDEC peripheral clock enable Set and reset by software. 0 (B_0x0): JPGDEC peripheral clock disabled (default after reset) 1 (B_0x1): JPGDEC peripheral clock enabled |
| FMCEN | FMC peripheral clocks enable Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock. 0 (B_0x0): FMC peripheral clocks disabled (default after reset) 1 (B_0x1): FMC peripheral clocks enabled |
| OCTOSPI1EN | OCTOSPI1 and OCTOSPI1 delay clock enable Set and reset by software. 0 (B_0x0): OCTOSPI1 and OCTOSPI1 delay clock disabled (default after reset) 1 (B_0x1): OCTOSPI1 and OCTOSPI1 delay clock enabled |
| SDMMC1EN | SDMMC1 and SDMMC1 delay clock enable Set and reset by software. 0 (B_0x0): SDMMC1 and SDMMC1 delay clock disabled (default after reset) 1 (B_0x1): SDMMC1 and SDMMC1 delay clock enabled |
| OCTOSPI2EN | OCTOSPI2 clock enable Set and reset by software. 0 (B_0x0): OCTOSPI2 and OCTOSPI2 delay clock disabled (default after reset) 1 (B_0x1): OCTOSPI2 OCTOSPI2 delay clock enabled |
| OCTOSPIMEN | OCTOSPIM clock enable Set and reset by software. 0 (B_0x0): OCTOSPIM clock disabled (default after reset) 1 (B_0x1): OCTOSPIM clock enabled |
| OTFD1EN | OTFD1 clock enable Set and reset by software. 0 (B_0x0): OTFD1 clock disabled (default after reset) 1 (B_0x1): OTFD1 clock enabled |
| OTFD2EN | OTFD2 clock enable Set and reset by software. 0 (B_0x0): OTFD2 clock disabled (default after reset) 1 (B_0x1): OTFD2 clock enabled |
| GFXMMUEN | GFXMMU clock enable Set and reset by software. 0 (B_0x0): GFXMMU clock disabled (default after reset) 1 (B_0x1): GFXMMU clock enabled |