stm32 /stm32h7 /STM32H7B0 /RCC /RCC_AHB4ENR

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Interpret as RCC_AHB4ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOAEN 0 (B_0x0)GPIOBEN 0 (B_0x0)GPIOCEN 0 (B_0x0)GPIODEN 0 (B_0x0)GPIOEEN 0 (B_0x0)GPIOFEN 0 (B_0x0)GPIOGEN 0 (B_0x0)GPIOHEN 0 (B_0x0)GPIOIEN 0 (B_0x0)GPIOJEN 0 (B_0x0)GPIOKEN 0 (B_0x0)BDMA2EN 0 (B_0x0)BKPRAMEN 0 (B_0x0)SRDSRAMEN

GPIOFEN=B_0x0, GPIOEEN=B_0x0, GPIOBEN=B_0x0, GPIOAEN=B_0x0, GPIOKEN=B_0x0, GPIODEN=B_0x0, GPIOCEN=B_0x0, GPIOIEN=B_0x0, GPIOJEN=B_0x0, BKPRAMEN=B_0x0, BDMA2EN=B_0x0, SRDSRAMEN=B_0x0, GPIOHEN=B_0x0, GPIOGEN=B_0x0

Fields

GPIOAEN

GPIOA peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOA peripheral clock disabled (default after reset)

1 (B_0x1): GPIOA peripheral clock enabled

GPIOBEN

GPIOB peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOB peripheral clock disabled (default after reset)

1 (B_0x1): GPIOB peripheral clock enabled

GPIOCEN

GPIOC peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOC peripheral clock disabled (default after reset)

1 (B_0x1): GPIOC peripheral clock enabled

GPIODEN

GPIOD peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOD peripheral clock disabled (default after reset)

1 (B_0x1): GPIOD peripheral clock enabled

GPIOEEN

GPIOE peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOE peripheral clock disabled (default after reset)

1 (B_0x1): GPIOE peripheral clock enabled

GPIOFEN

GPIOF peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOF peripheral clock disabled (default after reset)

1 (B_0x1): GPIOF peripheral clock enabled

GPIOGEN

GPIOG peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOG peripheral clock disabled (default after reset)

1 (B_0x1): GPIOG peripheral clock enabled

GPIOHEN

GPIOH peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOH peripheral clock disabled (default after reset)

1 (B_0x1): GPIOH peripheral clock enabled

GPIOIEN

GPIOI peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOI peripheral clock disabled (default after reset)

1 (B_0x1): GPIOI peripheral clock enabled

GPIOJEN

GPIOJ peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOJ peripheral clock disabled (default after reset)

1 (B_0x1): GPIOJ peripheral clock enabled

GPIOKEN

GPIOK peripheral clock enable Set and reset by software.

0 (B_0x0): GPIOK peripheral clock disabled (default after reset)

1 (B_0x1): GPIOK peripheral clock enabled

BDMA2EN

SmartRun domain DMA and DMAMUX clock enable Set and reset by software.

0 (B_0x0): BDMA2 and DMAMUX2 clock disabled (default after reset)

1 (B_0x1): BDMA2 and DMAMUX2 clock enabled

BKPRAMEN

Backup RAM clock enable Set and reset by software.

0 (B_0x0): Backup RAM clock disabled (default after reset)

1 (B_0x1): Backup RAM clock enabled

SRDSRAMEN

SmartRun domain SRAM clock enable Set and reset by software.

0 (B_0x0): SRDSRAM clock disabled (default after reset)

1 (B_0x1): SRDSRAM clock enabled

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