CRSEN=B_0x0, FDCANEN=B_0x0, MDIOSEN=B_0x0, OPAMPEN=B_0x0, SWPMIEN=B_0x0
| CRSEN | clock recovery system peripheral clock enable Set and reset by software. 0 (B_0x0): CRS peripheral clock disabled (default after reset) 1 (B_0x1): CRS peripheral clock enabled |
| SWPMIEN | SWPMI peripheral clocks enable Set and reset by software. 0 (B_0x0): SWPMI peripheral clocks disabled (default after reset) 1 (B_0x1): SWPMI peripheral clocks enabled: |
| OPAMPEN | OPAMP peripheral clock enable Set and reset by software. 0 (B_0x0): OPAMP peripheral clock disabled (default after reset) 1 (B_0x1): OPAMP peripheral clock enabled |
| MDIOSEN | MDIOS peripheral clock enable Set and reset by software. 0 (B_0x0): MDIOS peripheral clock disabled (default after reset) 1 (B_0x1): MDIOS peripheral clock enabled |
| FDCANEN | FDCAN peripheral clocks enable Set and reset by software. The peripheral clocks of the FDCAN are the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): FDCAN peripheral clocks disabled (default after reset) 1 (B_0x1): FDCAN peripheral clocks enabled: |