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stm32 /stm32h7 /STM32H7B0 /RCC /RCC_APB1HRSTR

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Interpret as RCC_APB1HRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CRSRST 0 (B_0x0)SWPMIRST 0 (B_0x0)OPAMPRST 0 (B_0x0)MDIOSRST 0 (B_0x0)FDCANRST

SWPMIRST=B_0x0, OPAMPRST=B_0x0, FDCANRST=B_0x0, CRSRST=B_0x0, MDIOSRST=B_0x0

Fields

CRSRST

clock recovery system reset Set and reset by software.

0 (B_0x0): does not reset CRS (default after reset)

1 (B_0x1): resets CRS
SWPMIRST

SWPMI block reset Set and reset by software.

0 (B_0x0): does not reset the SWPMI block (default after reset)

1 (B_0x1): resets the SWPMI block
OPAMPRST

OPAMP block reset Set and reset by software.

0 (B_0x0): does not reset the OPAMP block (default after reset)

1 (B_0x1): resets the OPAMP block
MDIOSRST

MDIOS block reset Set and reset by software.

0 (B_0x0): does not reset the MDIOS block (default after reset)

1 (B_0x1): resets the MDIOS block
FDCANRST

FDCAN block reset Set and reset by software.

0 (B_0x0): does not reset the FDCAN block (default after reset)

1 (B_0x1): resets the FDCAN block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32