USART1EN=B_0x0, TIM17EN=B_0x0, DFSDM1EN=B_0x0, TIM15EN=B_0x0, SPI4EN=B_0x0, TIM16EN=B_0x0, SPI1EN=B_0x0, TIM1EN=B_0x0, SAI2EN=B_0x0, SAI1EN=B_0x0, SPI5EN=B_0x0, USART10EN=B_0x0, TIM8EN=B_0x0, UART9EN=B_0x0, USART6EN=B_0x0
| TIM1EN | TIM1 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM1 peripheral clock disabled (default after reset) 1 (B_0x1): TIM1 peripheral clock enabled |
| TIM8EN | TIM8 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM8 peripheral clock disabled (default after reset) 1 (B_0x1): TIM8 peripheral clock enabled |
| USART1EN | USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART1 peripheral clocks disabled (default after reset) 1 (B_0x1): USART1 peripheral clocks enabled: |
| USART6EN | USART6 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART6 peripheral clocks disabled (default after reset) 1 (B_0x1): USART6 peripheral clocks enabled: |
| UART9EN | UART9 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): UART9 peripheral clocks disabled (default after reset) 1 (B_0x1): UART9 peripheral clocks enabled: |
| USART10EN | USART10 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART10 peripheral clocks disabled (default after reset) 1 (B_0x1): USART10 peripheral clocks enabled: |
| SPI1EN | SPI1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI1 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI1 peripheral clocks enabled: |
| SPI4EN | SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI4 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI4 peripheral clocks enabled: |
| TIM15EN | TIM15 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM15 peripheral clock disabled (default after reset) 1 (B_0x1): TIM15 peripheral clock enabled |
| TIM16EN | TIM16 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM16 peripheral clock disabled (default after reset) 1 (B_0x1): TIM16 peripheral clock enabled |
| TIM17EN | TIM17 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM17 peripheral clock disabled (default after reset) 1 (B_0x1): TIM17 peripheral clock enabled |
| SPI5EN | SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI5 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI5 peripheral clocks enabled: |
| SAI1EN | SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SAI1 peripheral clocks disabled (default after reset) 1 (B_0x1): SAI1 peripheral clocks enabled: |
| SAI2EN | SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SAI2 peripheral clocks disabled (default after reset) 1 (B_0x1): SAI2 peripheral clocks enabled |
| DFSDM1EN | DFSDM1 peripheral clocks enable Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, 0 (B_0x0): DFSDM1 peripheral clocks disabled (default after reset) 1 (B_0x1): DFSDM1 peripheral clocks enabled |