SPI5LPEN=B_0x0, TIM8LPEN=B_0x0, SPI1LPEN=B_0x0, SPI4LPEN=B_0x0, DFSDM1LPEN=B_0x0, TIM1LPEN=B_0x0, TIM15LPEN=B_0x0, SAI1LPEN=B_0x0, SAI2LPEN=B_0x0, TIM16LPEN=B_0x0, USART6LPEN=B_0x0, TIM17LPEN=B_0x0, USART1LPEN=B_0x0, USART10LPEN=B_0x0, UART9LPEN=B_0x0
| TIM1LPEN | TIM1 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM1 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM1 peripheral clock enabled during CSleep mode (default after reset) |
| TIM8LPEN | TIM8 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM8 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM8 peripheral clock enabled during CSleep mode (default after reset) |
| USART1LPEN | USART1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART1 peripheral clocks disabled during CSleep mode 1 (B_0x1): USART1 peripheral clocks enabled during CSleep mode (default after reset) |
| USART6LPEN | USART6 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART6 peripheral clocks disabled during CSleep mode 1 (B_0x1): USART6 peripheral clocks enabled during CSleep mode (default after reset) |
| UART9LPEN | UART9 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): UART9 peripheral clocks disabled during CSleep mode 1 (B_0x1): UART9 peripheral clocks enabled during CSleep mode (default after reset) |
| USART10LPEN | USART10 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): USART10 peripheral clocks disabled during CSleep mode 1 (B_0x1): USART10 peripheral clocks enabled during CSleep mode (default after reset) |
| SPI1LPEN | SPI1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI1 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI1 peripheral clocks enabled during CSleep mode (default after reset) |
| SPI4LPEN | SPI4 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI4 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI4 peripheral clocks enabled during CSleep mode (default after reset) |
| TIM15LPEN | TIM15 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM15 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM15 peripheral clock enabled during CSleep mode (default after reset) |
| TIM16LPEN | TIM16 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM16 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM16 peripheral clock enabled during CSleep mode (default after reset) |
| TIM17LPEN | TIM17 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): TIM17 peripheral clock disabled during CSleep mode 1 (B_0x1): TIM17 peripheral clock enabled during CSleep mode (default after reset) |
| SPI5LPEN | SPI5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SPI5 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI5 peripheral clocks enabled during CSleep mode (default after reset) |
| SAI1LPEN | SAI1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SAI1 peripheral clocks disabled during CSleep mode 1 (B_0x1): SAI1 peripheral clocks enabled during CSleep mode (default after reset) |
| SAI2LPEN | SAI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI23EL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock. 0 (B_0x0): SAI2 peripheral clocks disabled during CSleep mode 1 (B_0x1): SAI2 peripheral clocks enabled during CSleep mode (default after reset) |
| DFSDM1LPEN | DFSDM1 peripheral clocks enable during CSleep mode Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock. 0 (B_0x0): DFSDM1 peripheral clocks disabled during CSleep mode 1 (B_0x1): DFSDM1 peripheral clocks enabled during CSleep mode (default after reset) |