VREFEN=B_0x0, COMP12EN=B_0x0, DTSEN=B_0x0, LPTIM2EN=B_0x0, SYSCFGEN=B_0x0, DFSDM2EN=B_0x0, SPI6EN=B_0x0, LPUART1EN=B_0x0, LPTIM3EN=B_0x0, DAC2EN=B_0x0, I2C4EN=B_0x0, RTCAPBEN=B_0x0
| SYSCFGEN | SYSCFG peripheral clock enable Set and reset by software. 0 (B_0x0): SYSCFG peripheral clock disabled (default after reset) 1 (B_0x1): SYSCFG peripheral clock enabled |
| LPUART1EN | LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPUART1 peripheral clocks disabled (default after reset) 1 (B_0x1): LPUART1 peripheral clocks enabled |
| SPI6EN | SPI6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): SPI6 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI6 peripheral clocks enabled |
| I2C4EN | I2C4 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): I2C4 peripheral clocks disabled (default after reset) 1 (B_0x1): I2C4 peripheral clocks enabled |
| LPTIM2EN | LPTIM2 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPTIM2 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM2 peripheral clocks enabled |
| LPTIM3EN | LPTIM3 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPTIM3 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM3 peripheral clocks enabled |
| DAC2EN | DAC2 (containing one converter) peripheral clock enable Set and reset by software. 0 (B_0x0): DAC2 peripheral clock disabled (default after reset) 1 (B_0x1): DAC2 peripheral clock enabled |
| COMP12EN | COMP1 and 2 peripheral clock enable Set and reset by software. 0 (B_0x0): COMP1 and 2 peripheral clock disabled (default after reset) 1 (B_0x1): COMP1 and 2 peripheral clock enabled |
| VREFEN | VREF peripheral clock enable Set and reset by software. 0 (B_0x0): VREF peripheral clock disabled (default after reset) 1 (B_0x1): VREF peripheral clock enabled |
| RTCAPBEN | RTC APB clock enable Set and reset by software. 0 (B_0x0): The register clock interface of the RTC (APB) is disabled 1 (B_0x1): The register clock interface of the RTC (APB) is enabled (default after reset) |
| DTSEN | Digital temperature sensor peripheral clock enable Set and reset by software. 0 (B_0x0): DTS peripheral clock disabled (default after reset) 1 (B_0x1): DTS peripheral clock enabled |
| DFSDM2EN | DFSDM2peripheral clock enable Set and reset by software. 0 (B_0x0): DFSDM2peripheral peripheral clock disabled (default after reset) 1 (B_0x1): DFSDM2peripheral peripheral clock enabled |