RTCAPBLPEN=B_0x0, VREFLPEN=B_0x0, LPTIM2LPEN=B_0x0, I2C4LPEN=B_0x0, SPI6LPEN=B_0x0, LPUART1LPEN=B_0x0, DFSDM2LPEN=B_0x0, COMP12LPEN=B_0x0, SYSCFGLPEN=B_0x0, LPTIM3LPEN=B_0x0, DAC2LPEN=B_0x0, DTSLPEN=B_0x0
| SYSCFGLPEN | SYSCFG peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): SYSCFG peripheral clock disabled during CSleep mode 1 (B_0x1): SYSCFG peripheral clock enabled during CSleep mode (default after reset) |
| LPUART1LPEN | LPUART1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPUART1 peripheral clocks disabled during CSleep mode 1 (B_0x1): LPUART1 peripheral clocks enabled during CSleep mode (default after reset) |
| SPI6LPEN | SPI6 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): SPI6 peripheral clocks disabled during CSleep mode 1 (B_0x1): SPI6 peripheral clocks enabled during CSleep mode (default after reset) |
| I2C4LPEN | I2C4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): I2C4 peripheral clocks disabled during CSleep mode 1 (B_0x1): I2C4 peripheral clocks enabled during CSleep mode (default after reset) |
| LPTIM2LPEN | LPTIM2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPTIM2 peripheral clocks disabled during CSleep mode 1 (B_0x1): LPTIM2 peripheral clocks enabled during CSleep mode (default after reset) |
| LPTIM3LPEN | LPTIM3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock. 0 (B_0x0): LPTIM3 peripheral clocks disabled during CSleep mode 1 (B_0x1): LPTIM3 peripheral clocks enabled during CSleep mode (default after reset) |
| DAC2LPEN | DAC2 (containing one converter) peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DAC2 peripheral clock disabled during CSleep mode 1 (B_0x1): DAC2 peripheral clock enabled during CSleep mode (default after reset) |
| COMP12LPEN | COMP1 and 2 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): COMP1 and 2 peripheral clock disabled during CSleep mode 1 (B_0x1): COMP1 and 2 peripheral clock enabled during CSleep mode (default after reset) |
| VREFLPEN | VREF peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): VREF peripheral clock disabled during CSleep mode 1 (B_0x1): VREF peripheral clock enabled during CSleep mode (default after reset) |
| RTCAPBLPEN | RTC APB clock enable during CSleep mode Set and reset by software. 0 (B_0x0): The register clock interface of the RTC (APB) is disabled during CSleep mode 1 (B_0x1): The register clock interface of the RTC (APB) is enabled during CSleep mode (default after reset) |
| DTSLPEN | temperature sensor peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DTS peripheral clock disabled during CSleep mode 1 (B_0x1): DTS peripheral clock enabled during CSleep mode (default after reset) |
| DFSDM2LPEN | DFSDM2 peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DFSDM2 peripheral clock disabled during CSleep mode 1 (B_0x1): DFSDM2 peripheral clock enabled during CSleep mode (default after reset) |