DFSDM1SEL=B_0x0, SAI2BSEL=B_0x0, SAI2ASEL=B_0x0, SPDIFRXSEL=B_0x0, SPI45SEL=B_0x0, SWPMISEL=B_0x0, SPI123SEL=B_0x0, FDCANSEL=B_0x0, SAI1SEL=B_0x0
RCC CPU domain kernel clock configuration register
| SAI1SEL | SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): pll1_q_ck selected as SAI1 and DFSDM1 Aclk kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as SAI1 and DFSDM1 Aclk kernel clock 2 (B_0x2): pll3_p_ck selected as SAI1 and DFSDM1 Aclk kernel clock 3 (B_0x3): I2S_CKIN selected as SAI1 and DFSDM1 Aclk kernel clock 4 (B_0x4): per_ck selected as SAI1 and DFSDM1 Aclk kernel clock |
| SAI2ASEL | SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see ). 0 (B_0x0): pll1_q_ck selected as SAI2 kernel clock A (default after reset) 1 (B_0x1): pll2_p_ck selected as SAI2 kernel clock A 2 (B_0x2): pll3_p_ck selected as SAI2 kernel clock A 3 (B_0x3): I2S_CKIN selected as SAI2 kernel clock A 4 (B_0x4): per_ck selected as SAI2 kernel clock A 5 (B_0x5): spdifrx_symb_ck selected as SAI2 kernel clock A |
| SAI2BSEL | SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see ). 0 (B_0x0): pll1_q_ck selected as SAI2 kernel clock B (default after reset) 1 (B_0x1): pll2_p_ck selected as SAI2 kernel clock B 2 (B_0x2): pll3_p_ck selected as SAI2 kernel clock B 3 (B_0x3): I2S_CKIN selected as SAI2 kernel clock B 4 (B_0x4): per_ck selected as SAI2 kernel clock B 5 (B_0x5): spdifrx_symb_ck selected as SAI2 kernel clock B |
| SPI123SEL | SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): pll1_q_ck selected as SPI/I2S1,2 and 3 kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as SPI/I2S1,2 and 3 kernel clock 2 (B_0x2): pll3_p_ck selected as SPI/I2S1,2 and 3 kernel clock 3 (B_0x3): I2S_CKIN selected as SPI/I2S1,2 and 3 kernel clock 4 (B_0x4): per_ck selected as SPI/I2S1,2 and 3 kernel clock |
| SPI45SEL | SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk2 clock selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck is selected as kernel clock 2 (B_0x2): pll3_q_ck is selected as kernel clock 3 (B_0x3): hsi_ker_ck is selected as kernel clock 4 (B_0x4): csi_ker_ck is selected as kernel clock 5 (B_0x5): hse_ck is selected as kernel clock |
| SPDIFRXSEL | SPDIFRX kernel clock source selection 0 (B_0x0): pll1_q_ck selected as SPDIFRX kernel clock (default after reset) 1 (B_0x1): pll2_r_ck selected as SPDIFRX kernel clock 2 (B_0x2): pll3_r_ck selected as SPDIFRX kernel clock 3 (B_0x3): hsi_ker_ck selected as SPDIFRX kernel clock |
| DFSDM1SEL | DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see ). 0 (B_0x0): rcc_pclk2 selected as DFSDM1 Clk kernel clock (default after reset) 1 (B_0x1): sys_ck selected as DFSDM1 Clk kernel clock |
| FDCANSEL | FDCAN kernel clock source selection Set and reset by software. 0 (B_0x0): hse_ck clock selected as FDCAN kernel clock (default after reset) 1 (B_0x1): pll1_q_ck selected as FDCAN kernel clock 2 (B_0x2): pll2_q_ck selected as FDCAN kernel clock 3 (B_0x3): reserved, the kernel clock is disabled |
| SWPMISEL | SWPMI kernel clock source selection Set and reset by software. 0 (B_0x0): rcc_pclk1 selected as SWPMI kernel clock (default after reset) 1 (B_0x1): hsi_ker_ck selected as SWPMI kernel clock |