stm32 /stm32h7 /STM32H7B0 /RCC /RCC_CDCCIPR

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Interpret as RCC_CDCCIPR

OCTOSPISEL=B_0x0, FMCSEL=B_0x0, CKPERSEL=B_0x0, SDMMCSEL=B_0x0

Description

RCC CPU domain kernel clock configuration register

Fields

FMCSEL	FMC kernel clock source selection 0 (B_0x0): rcc_hclk3 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll1_q_ck selected as kernel peripheral clock 2 (B_0x2): pll2_r_ck selected as kernel peripheral clock 3 (B_0x3): per_ck selected as kernel peripheral clock
OCTOSPISEL	OCTOSPI kernel clock source selection 0 (B_0x0): rcc_hclk3 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll1_q_ck selected as kernel peripheral clock 2 (B_0x2): pll2_r_ck selected as kernel peripheral clock 3 (B_0x3): per_ck selected as kernel peripheral clock
SDMMCSEL	SDMMC kernel clock source selection 0 (B_0x0): pll1_q_ck selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_r_ck selected as kernel peripheral clock
CKPERSEL	per_ck clock source selection 0 (B_0x0): hsi_ker_ck selected as per_ck clock (default after reset) 1 (B_0x1): csi_ker_ck selected as per_ck clock 2 (B_0x2): hse_ck selected as per_ck clock 3 (B_0x3): reserved, the per_ck clock is disabled

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