| HPRE | CPU domain AHB prescaler Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: rcc_hclk3 = sys_cdcpre_ck (default after reset) Note: The clocks are divided by the new prescaler factor from1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after HPRE update. Note: Note also that rcc_hclk3 = rcc_aclk. 8 (B_0x8): rcc_hclk3 = sys_cdcpre_ck / 2 9 (B_0x9): rcc_hclk3 = sys_cdcpre_ck / 4 10 (B_0xA): rcc_hclk3 = sys_cdcpre_ck / 8 11 (B_0xB): rcc_hclk3 = sys_cdcpre_ck / 16 12 (B_0xC): rcc_hclk3 = sys_cdcpre_ck / 64 13 (B_0xD): rcc_hclk3 = sys_cdcpre_ck / 128 14 (B_0xE): rcc_hclk3 = sys_cdcpre_ck / 256 15 (B_0xF): rcc_hclk3 = sys_cdcpre_ck / 512 |
| CDPPRE | CPU domain APB3 prescaler Set and reset by software to control the division factor of rcc_pclk3. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after CDPPRE write. 0xx: rcc_pclk3 = rcc_hclk3 (default after reset) 4 (B_0x4): rcc_pclk3 = rcc_hclk3 / 2 5 (B_0x5): rcc_pclk3 = rcc_hclk3 / 4 6 (B_0x6): rcc_pclk3 = rcc_hclk3 / 8 7 (B_0x7): rcc_pclk3 = rcc_hclk3 / 16 |
| CDCPRE | CPU domain core prescaler Set and reset by software to control the CPU domain CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset) 8 (B_0x8): sys_ck divided by 2 9 (B_0x9): sys_ck divided by 4 10 (B_0xA): sys_ck divided by 8 11 (B_0xB): sys_ck divided by 16 12 (B_0xC): sys_ck divided by 64 13 (B_0xD): sys_ck divided by 128 14 (B_0xE): sys_ck divided by 256 15 (B_0xF): sys_ck divided by 512 |