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stm32 /stm32h7 /STM32H7B0 /RCC /RCC_CDCFGR2

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Interpret as RCC_CDCFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CDPPRE1 0CDPPRE2

Fields

CDPPRE1

CPU domain APB1 prescaler Set and reset by software to control the CPU domain APB1 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE1 write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)

4 (B_0x4): rcc_pclk1 = rcc_hclk1 / 2

5 (B_0x5): rcc_pclk1 = rcc_hclk1 / 4

6 (B_0x6): rcc_pclk1 = rcc_hclk1 / 8

7 (B_0x7): rcc_pclk1 = rcc_hclk1 / 16
CDPPRE2

CPU domain APB2 prescaler Set and reset by software to control the CPU domain APB2 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 (default after reset)

4 (B_0x4): rcc_pclk2 = rcc_hclk1 / 2

5 (B_0x5): rcc_pclk2 = rcc_hclk1 / 4

6 (B_0x6): rcc_pclk2 = rcc_hclk1 / 8

7 (B_0x7): rcc_pclk2 = rcc_hclk1 / 16

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32