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stm32 /stm32h7 /STM32H7B0 /RCC /RCC_CIER

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Interpret as RCC_CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDYIE 0 (B_0x0)LSERDYIE 0 (B_0x0)HSIRDYIE 0 (B_0x0)HSERDYIE 0 (B_0x0)CSIRDYIE 0 (B_0x0)HSI48RDYIE 0 (B_0x0)PLL1RDYIE 0 (B_0x0)PLL2RDYIE 0 (B_0x0)PLL3RDYIE 0 (B_0x0)LSECSSIE

PLL1RDYIE=B_0x0, LSIRDYIE=B_0x0, PLL2RDYIE=B_0x0, HSI48RDYIE=B_0x0, CSIRDYIE=B_0x0, HSERDYIE=B_0x0, LSECSSIE=B_0x0, HSIRDYIE=B_0x0, LSERDYIE=B_0x0, PLL3RDYIE=B_0x0

Fields

LSIRDYIE

LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.

0 (B_0x0): LSI ready interrupt disabled (default after reset)

1 (B_0x1): LSI ready interrupt enabled
LSERDYIE

LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.

0 (B_0x0): LSE ready interrupt disabled (default after reset)

1 (B_0x1): LSE ready interrupt enabled
HSIRDYIE

HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.

0 (B_0x0): HSI ready interrupt disabled (default after reset)

1 (B_0x1): HSI ready interrupt enabled
HSERDYIE

HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.

0 (B_0x0): HSE ready interrupt disabled (default after reset)

1 (B_0x1): HSE ready interrupt enabled
CSIRDYIE

CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.

0 (B_0x0): CSI ready interrupt disabled (default after reset)

1 (B_0x1): CSI ready interrupt enabled
HSI48RDYIE

HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.

0 (B_0x0): HSI48 ready interrupt disabled (default after reset)

1 (B_0x1): HSI48 ready interrupt enabled
PLL1RDYIE

PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock.

0 (B_0x0): PLL1 lock interrupt disabled (default after reset)

1 (B_0x1): PLL1 lock interrupt enabled
PLL2RDYIE

PLL2 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL2 lock.

0 (B_0x0): PLL2 lock interrupt disabled (default after reset)

1 (B_0x1): PLL2 lock interrupt enabled
PLL3RDYIE

PLL3 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL3 lock.

0 (B_0x0): PLL3 lock interrupt disabled (default after reset)

1 (B_0x1): PLL3 lock interrupt enabled
LSECSSIE

LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator.

0 (B_0x0): LSE CSS interrupt disabled (default after reset)

1 (B_0x1): LSE CSS interrupt enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32