ECCRAMCKG=B_0x0, FLIFTCKG=B_0x0, LTDCCKG=B_0x0, AHB34CKG=B_0x0, AHB12CKG=B_0x0, DMA2DCKG=B_0x0, GFXMMUMCKG=B_0x0, AXIRAM2CKG=B_0x0, GFXMMUSCKG=B_0x0, AXIRAM1CKG=B_0x0, OCTOSPI2CKG=B_0x0, EXTICKG=B_0x0, OCTOSPI1CKG=B_0x0, AXICKG=B_0x0, CPUCKG=B_0x0, JTAGCKG=B_0x0, AHBCKG=B_0x0, FMCCKG=B_0x0, AXIRAM3CKG=B_0x0, MDMACKG=B_0x0, SDMMCCKG=B_0x0
RCC AXI clocks gating enable register
| AXICKG | AXI interconnect matrix clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI interconnect matrix clock is enabled on bus transaction request. |
| AHBCKG | AXI master AHB clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix master AHB clock is enabled on bus transaction request. |
| CPUCKG | AXI master CPU clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix master CPU clock is enabled on bus transaction request. |
| SDMMCCKG | AXI master SDMMC clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix master SDMMC clock is enabled on bus transaction request. |
| MDMACKG | AXI master MDMA clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix master MDMA clock is enabled on bus transaction request. |
| DMA2DCKG | AXI master DMA2D clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix master DMA2D clock is enabled on bus transaction request. |
| LTDCCKG | AXI master LTDC clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix master LTDC clock is enabled on bus transaction request. |
| GFXMMUMCKG | AXI master GFXMMU clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix master GFXMMU clock is enabled on bus transaction request. |
| AHB12CKG | AXI slave AHB12 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix slave AHB12 clock is enabled on bus transaction request. |
| AHB34CKG | AXI slave AHB34 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix slave AHB34 clock is enabled on bus transaction request. |
| FLIFTCKG | AXI slave Flash interface (FLIFT) clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave FLIFT clock is enabled on bus transaction request. |
| OCTOSPI2CKG | AXI slave OCTOSPI2 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave OCTOSPI2 clock is enabled on bus transaction request. |
| FMCCKG | AXI slave FMC clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave FMC clock is enabled on bus transaction request. |
| OCTOSPI1CKG | AXI slave OCTOSPI1 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave OCTOSPI1 clock is enabled on bus transaction request. |
| AXIRAM1CKG | AXI slave SRAM1 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave SRAM1 clock is enabled on bus transaction request. |
| AXIRAM2CKG | AXI matrix slave SRAM2 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave SRAM2 clock is enabled on bus transaction request. |
| AXIRAM3CKG | AXI matrix slave SRAM3 clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The AXI matrix slave SRAM3 clock is enabled on bus transaction request. |
| GFXMMUSCKG | AXI matrix slave GFXMMU clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled 1 (B_0x1): The clock gating is enabled. The AXI matrix slave GFXMMU clock is enabled on bus transaction request. |
| ECCRAMCKG | RAM error code correction (ECC) clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The ECC clock is enabled only during a RAM access. |
| EXTICKG | EXTI clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The clock is enabled after an event detection and stopped again when the event flag is cleared. |
| JTAGCKG | JTAG automatic clock gating This bit is set and reset by software. 0 (B_0x0): The clock gating is disabled. The clock is always enabled. 1 (B_0x1): The clock gating is enabled. The clock is disabled except if a JTAG connection has been detected |