RCC_CSR

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Interpret as RCC_CSR

LSION=B_0x0, LSIRDY=B_0x0

Description

RCC clock control and status register

Fields

LSION

LSI oscillator enable Set and reset by software.

0 (B_0x0): LSI is OFF (default after reset)

1 (B_0x1): LSI is ON

LSIRDY

LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.

0 (B_0x0): LSI clock is not ready (default after reset)

1 (B_0x1): LSI clock is ready

Links

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