DIVR1EN=B_0x0, PLL3VCOSEL=B_0x0, PLL3RGE=B_0x0, PLL2VCOSEL=B_0x0, DIVR3EN=B_0x0, DIVQ3EN=B_0x0, DIVQ1EN=B_0x0, DIVP1EN=B_0x0, DIVP3EN=B_0x0, DIVR2EN=B_0x0, DIVQ2EN=B_0x0, PLL1RGE=B_0x0, DIVP2EN=B_0x0, PLL2RGE=B_0x0, PLL1VCOSEL=B_0x0
| PLL1FRACEN | PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. Refer to for additional information. |
| PLL1VCOSEL | PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. These bits must be written before enabling the PLL1. 0 (B_0x0): wide VCO range from 128 to 560 MHz (default after reset) 1 (B_0x1): medium VCO range from 150 to 420 MHz |
| PLL1RGE | PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 0 (B_0x0): PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL2FRACEN | PLL2 fractional latch enable Set and reset by software to latch the content of FRACN2 into the sigma-delta modulator. In order to latch the FRACN2 value into the sigma-delta modulator, PLL2FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN2 into the modulator. Refer to for additional information. |
| PLL2VCOSEL | PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. 0 (B_0x0): wide VCO range 128 to 560 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| PLL2RGE | PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 0 (B_0x0): PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz |
| PLL3FRACEN | PLL3 fractional latch enable Set and reset by software to latch the content of FRACN3 into the sigma-delta modulator. In order to latch the FRACN3 value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN3 into the modulator. Refer to for additional information. |
| PLL3VCOSEL | PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3. 0 (B_0x0): wide VCO range 128 to 560 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| PLL3RGE | PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. These bits must be written before enabling the PLL3. 0 (B_0x0): PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz |
| DIVP1EN | PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 0 (B_0x0): pll1_p_ck output disabled 1 (B_0x1): pll1_p_ck output enabled (default after reset) |
| DIVQ1EN | PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1_q_ck output disabled 1 (B_0x1): pll1_q_ck output enabled (default after reset) |
| DIVR1EN | PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1_r_ck output disabled 1 (B_0x1): pll1_r_ck output enabled (default after reset) |
| DIVP2EN | PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll2_p_ck output disabled 1 (B_0x1): pll2_p_ck output enabled (default after reset) |
| DIVQ2EN | PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). 0 (B_0x0): pll2_q_ck output disabled 1 (B_0x1): pll2_q_ck output enabled (default after reset) |
| DIVR2EN | PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). 0 (B_0x0): pll2_r_ck output disabled 1 (B_0x1): pll2_r_ck output enabled (default after reset) |
| DIVP3EN | PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll3_p_ck output disabled 1 (B_0x1): pll3_p_ck output enabled (default after reset) |
| DIVQ3EN | PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). 0 (B_0x0): pll3_q_ck output disabled 1 (B_0x1): pll3_q_ck output enabled (default after reset) |
| DIVR3EN | PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). 0 (B_0x0): pll3_r_ck output disabled 1 (B_0x1): pll3_r_ck output enabled (default after reset) |