DIVM3=B_0x0, DIVM2=B_0x0, PLLSRC=B_0x0, DIVM1=B_0x0
| PLLSRC | DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLLSRC must be set to '11â. 0 (B_0x0): HSI selected as PLL clock (hsi_ck) (default after reset) 1 (B_0x1): CSI selected as PLL clock (csi_ck) 2 (B_0x2): HSE selected as PLL clock (hse_ck) 3 (B_0x3): no clock send to DIVMx divider and PLLs |
| DIVM1 | prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ONÂ =Â 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. … … 0 (B_0x0): prescaler disabled 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 (default after reset) 63 (B_0x3F): division by 63 |
| DIVM2 | prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ONÂ =Â 1). In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0. … … 0 (B_0x0): prescaler disabled 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 (default after reset) 63 (B_0x3F): division by 63 |
| DIVM3 | prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ONÂ =Â 1). In order to save power when PLL3 is not used, the value of DIVM3 must be set to 0. … … 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 (default after reset) 63 (B_0x3F): division by 63 |