LPWRRSTF=B_0x0, PORRSTF=B_0x0, IWDGRSTF=B_0x0, RMVF=B_0x0, SFTRSTF=B_0x0, WWDGRSTF=B_0x0, CDRSTF=B_0x0, PINRSTF=B_0x0, BORRSTF=B_0x0
RCC reset status register
| RMVF | remove reset flag Set and reset by software to reset the value of the reset flags. 0 (B_0x0): reset of the reset flags not activated (default after power-on reset) 1 (B_0x1): resets the value of the reset flags |
| CDRSTF | CPU domain power-switch reset flag Reset by software by writing the RMVF bit. Set by hardware when a the CPU domain exits from DStop or after of power-on reset. Set also when the CPU domain exists DStop2 but only when a pad reset has occurred during DStop2 (PINRST bit also set by hardware) 0 (B_0x0): no CPU domain power-switch reset occurred 1 (B_0x1): CPU domain power-switch (ePOD2) reset occurred (default after power-on reset) |
| BORRSTF | BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 0 (B_0x0): no BOR reset occurred 1 (B_0x1): BOR reset occurred (default after power-on reset) |
| PINRSTF | pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 0 (B_0x0): no reset from pin occurred 1 (B_0x1): reset from pin occurred (default after power-on reset) |
| PORRSTF | POR/PDR reset flag Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. 0 (B_0x0): no POR/PDR reset occurred 1 (B_0x1): POR/PDR reset occurred (default after power-on reset) |
| SFTRSTF | system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. 0 (B_0x0): no CPU software reset occurred (default after power-on reset) 1 (B_0x1): a system reset has been generated by the CPU |
| IWDGRSTF | independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 0 (B_0x0): no independent watchdog reset occurred (default after power-on reset) 1 (B_0x1): independent watchdog reset occurred |
| WWDGRSTF | window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 0 (B_0x0): no window watchdog reset occurred from WWDG (default after power-on reset) 1 (B_0x1): window watchdog reset occurred from WWDG |
| LPWRRSTF | reset due to illegal CD DStop or CD DStop2 or CPU CStop flag Reset by software by writing the RMVF bit. Set by hardware when the CPU domain goes erroneously in DStop or DStop2, or when the CPU goes erroneously in CStop. 0 (B_0x0): no illegal reset occurred (default after power-on reset) 1 (B_0x1): illegal CD DStop or CD DStop2 or CPU CStop reset occurred |