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stm32 /stm32h7 /STM32H7B0 /RCC /RCC_SRDAMR

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Interpret as RCC_SRDAMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BDMA2AMEN 0 (B_0x0)GPIOAMEN 0 (B_0x0)LPUART1AMEN 0 (B_0x0)SPI6AMEN 0 (B_0x0)I2C4AMEN 0 (B_0x0)LPTIM2AMEN 0 (B_0x0)LPTIM3AMEN 0 (B_0x0)DAC2AMEN 0 (B_0x0)COMP12AMEN 0 (B_0x0)VREFAMEN 0 (B_0x0)RTCAMEN 0 (B_0x0)DTSAMEN 0 (B_0x0)DFSDM2AMEN 0 (B_0x0)BKPRAMAMEN 0 (B_0x0)SRDSRAMAMEN

SPI6AMEN=B_0x0, SRDSRAMAMEN=B_0x0, LPTIM3AMEN=B_0x0, COMP12AMEN=B_0x0, VREFAMEN=B_0x0, DTSAMEN=B_0x0, DFSDM2AMEN=B_0x0, DAC2AMEN=B_0x0, BKPRAMAMEN=B_0x0, GPIOAMEN=B_0x0, I2C4AMEN=B_0x0, LPUART1AMEN=B_0x0, LPTIM2AMEN=B_0x0, BDMA2AMEN=B_0x0, RTCAMEN=B_0x0

Description

RCC SmartRun domain Autonomous mode register

Fields

BDMA2AMEN

SmartRun domain DMA and DMAMUX Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): BDMA2 and DMAMUX2 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): BDMA2 and DMAMUX2 peripheral clocks enabled when the SmartRun domain is in Run.
GPIOAMEN

GPIO Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): GPIO peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): GPIO peripheral clocks enabled when the SmartRun domain is in Run.
LPUART1AMEN

LPUART1 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): LPUART1 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): LPUART1 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.
SPI6AMEN

SPI6 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): SPI6 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): SPI6 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.
I2C4AMEN

I2C4 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): I2C4 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): I2C4 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.
LPTIM2AMEN

LPTIM2 Autonomous mode enable Set and reset by software. Refer to for additional information

0 (B_0x0): LPTIM2 peripheral clocks are disabled when the CPU is in CStop (default after reset)

1 (B_0x1): LPTIM2 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.
LPTIM3AMEN

LPTIM3 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): LPTIM3 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): LPTIM3 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock is enabled when the SmartRun domain is in Stop mode.
DAC2AMEN

DAC2 (containing one converter) Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): DAC2 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): DAC2 peripheral clocks enabled when the SmartRun domain is in Run.
COMP12AMEN

COMP1 and 2 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): COMP1 and 2 peripheral clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): COMP1 and 2 peripheral clocks enabled when the SmartRun domain is in Run.
VREFAMEN

VREF Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): VREF clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): VREF clocks enabled when the SmartRun domain is in Run or Stop mode.
RTCAMEN

RTC Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): RTC bus clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): RTC bus clocks enabled when the SmartRun domain is in Run.
DTSAMEN

Digital temperature sensor Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): DTS clocks disabled when the CPU is in CStop (default after reset)

1 (B_0x1): DTS clocks enabled when the SmartRun domain is in Run.
DFSDM2AMEN

DFSDM2 Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): DFSDM2 clock disabled when the CPU is in CStop (default after reset)

1 (B_0x1): DFSDM2 peripheral clocks enabled when the SmartRun domain is in Run mode. Kernel clock enabled when the SmartRun domain is in Stop mode.
BKPRAMAMEN

Backup RAM Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): Backup RAM clock disabled when the CPU is in CStop (default after reset)

1 (B_0x1): Backup RAM clock enabling is controlled by the SmartRun domain state.
SRDSRAMAMEN

SmartRun domain SRAM Autonomous mode enable Set and reset by software. Refer to for additional information.

0 (B_0x0): SRDSRAM clock disabled when the CPU is in CStop (default after reset)

1 (B_0x1): SRDSRAM bus clock enabled when the SmartRun domain is in Run.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32