RegViz: Visualize RCC_SRDCCIPR Bitfield

stm32 /stm32h7 /STM32H7B0 /RCC /RCC_SRDCCIPR

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Interpret as RCC_SRDCCIPR

SPI6SEL=B_0x0, LPTIM2SEL=B_0x0, I2C4SEL=B_0x0, LPTIM3SEL=B_0x0, DFSDM2SEL=B_0x0, LPUART1SEL=B_0x0, ADCSEL=B_0x0

Description

RCC SmartRun domain kernel clock configuration register

Fields

LPUART1SEL	LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk4 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel peripheral clock 2 (B_0x2): pll3_q_ck selected as kernel peripheral clock 3 (B_0x3): hsi_ker_ck selected as kernel peripheral clock 4 (B_0x4): csi_ker_ck selected as kernel peripheral clock 5 (B_0x5): lse_ck selected as kernel peripheral clock
I2C4SEL	I2C4 kernel clock source selection Set and reset by software. 0 (B_0x0): rcc_pclk4 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll3_r_ck selected as kernel peripheral clock 2 (B_0x2): hsi_ker_ck selected as kernel peripheral clock 3 (B_0x3): csi_ker_ck selected as kernel peripheral clock
LPTIM2SEL	LPTIM2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk4 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_p_ck selected as kernel peripheral clock 2 (B_0x2): pll3_r_ck selected as kernel peripheral clock 3 (B_0x3): lse_ck selected as kernel peripheral clock 4 (B_0x4): lsi_ck selected as kernel peripheral clock 5 (B_0x5): per_ck selected as kernel peripheral clock
LPTIM3SEL	LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk4 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_p_ck selected as kernel peripheral clock 2 (B_0x2): pll3_r_ck selected as kernel peripheral clock 3 (B_0x3): lse_ck selected as kernel peripheral clock 4 (B_0x4): lsi_ck selected as kernel peripheral clock 5 (B_0x5): per_ck selected as kernel peripheral clock
ADCSEL	SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pll2_p_ck selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll3_r_ck selected as kernel peripheral clock 2 (B_0x2): per_ck selected as kernel peripheral clock
DFSDM2SEL	DFSDM2 kernel Clk clock source selection Set and reset by software. Note: The DFSDM2 Aclk clock source selection is done by SPI6SEL (see and ). 0 (B_0x0): rcc_pclk4 selected as DFSDM2 Clk kernel clock (default after reset) 1 (B_0x1): sys_ck selected as DFSDM2 Clk kernel clock
SPI6SEL	SPI6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk4 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel peripheral clock 2 (B_0x2): pll3_q_ck selected as kernel peripheral clock 3 (B_0x3): hsi_ker_ck selected as kernel peripheral clock 4 (B_0x4): csi_ker_ck selected as kernel peripheral clock 5 (B_0x5): hse_ck selected as kernel peripheral clock 6 (B_0x6): I2S_CKIN selected as kernel peripheral clock

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