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stm32 /stm32h7 /STM32H7B0 /TIM2 /CCMR2_Output

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Interpret as CCMR2_Output

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC3S 0 (OC3FE)OC3FE 0 (OC3PE)OC3PE 0OC3M0 (OC3CE)OC3CE 0CC4S 0 (OC4FE)OC4FE 0 (OC4PE)OC4PE 0OC4M0 (OC4CE)OC4CE 0 (OC3M_3)OC3M_3 0 (OC4M_3)OC4M_3

Description

capture/compare mode register 2 (output mode)

Fields

CC3S

CC3S
OC3FE

OC3FE
OC3PE

OC3PE
OC3M

OC3M
OC3CE

OC3CE
CC4S

CC4S
OC4FE

OC4FE
OC4PE

OC4PE
OC4M

OC4M
OC4CE

OC4CE
OC3M_3

Output Compare 1 mode - bit 3
OC4M_3

Output Compare 2 mode - bit 3

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32