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stm32 /stm32h7 /STM32H7B3 /DBGMCU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBGSLEEP_CD)DBGSLEEP_CD 0 (DBGSTOP_CD)DBGSTOP_CD 0 (DBGSTBY_CD)DBGSTBY_CD 0 (DBGSTOP_SRD)DBGSTOP_SRD 0 (DBGSTBY_SRD)DBGSTBY_SRD 0 (TRACECLKEN)TRACECLKEN 0 (CDDBGCKEN)CDDBGCKEN 0 (SRDDBGCKEN)SRDDBGCKEN 0 (TRGOEN)TRGOEN

Description

DBGMCU Configuration Register

Fields

DBGSLEEP_CD

Allow D1 domain debug in Sleep mode
DBGSTOP_CD

Allow D1 domain debug in Stop mode
DBGSTBY_CD

Allow D1 domain debug in Standby mode
DBGSTOP_SRD

debug in SmartRun domain Stop mode
DBGSTBY_SRD

debug in SmartRun domain Standby mode
TRACECLKEN

Trace port clock enable
CDDBGCKEN

CPU domain debug clock enable
SRDDBGCKEN

SmartRun domain debug clock enable
TRGOEN

External trigger output enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32