stm32 /stm32h7 /STM32H7B3 /DFSDM1 /DFSDM_CH1CFGR1

Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).

0 (B_0x0): SPI with rising edge to strobe data

1 (B_0x1): SPI with falling edge to strobe data

2 (B_0x2): Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1

3 (B_0x3): Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0

SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

0 (B_0x0): clock coming from external CKINy input - sampling point according SITP[1:0]

1 (B_0x1): clock coming from internal CKOUT output - sampling point according SITP[1:0]

Short-circuit detector enable on channel y

0 (B_0x0): Input channel y will not be guarded by the short-circuit detector

1 (B_0x1): Input channel y will be continuously guarded by the short-circuit detector

Clock absence detector enable on channel y

0 (B_0x0): Clock absence detector disabled on channel y

1 (B_0x1): Clock absence detector enabled on channel y

Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.

0 (B_0x0): Channel y disabled

1 (B_0x1): Channel y enabled

Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

0 (B_0x0): Channel inputs are taken from pins of the same channel y.

1 (B_0x1): Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).

Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

0 (B_0x0): Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected.

1 (B_0x1): Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register.

Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

0 (B_0x0): Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.

1 (B_0x1): Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:

Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -

0 (B_0x0): Output clock generation is disabled (CKOUT signal is set to low state)

Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)

0 (B_0x0): Source for output clock is from system clock

1 (B_0x1): Source for output clock is from audio clock

Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0…7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0…7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)

0 (B_0x0): DFSDM interface disabled

1 (B_0x1): DFSDM interface enabled