RCIP=B_0x0, JCIP=B_0x0, JEOCF=B_0x0, AWDF=B_0x0, ROVRF=B_0x0, JOVRF=B_0x0, REOCF=B_0x0
| JEOCF | End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR. 0 (B_0x0): No injected conversion has completed 1 (B_0x1): An injected conversion has completed and its data may be read |
| REOCF | End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR. 0 (B_0x0): No regular conversion has completed 1 (B_0x1): A regular conversion has completed and its data may be read |
| JOVRF | Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register. 0 (B_0x0): No injected conversion overrun has occurred 1 (B_0x1): An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already '1â. JDATAR is not affected by overruns |
| ROVRF | Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register. 0 (B_0x0): No regular conversion overrun has occurred 1 (B_0x1): A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already '1â. RDATAR is not affected by overruns |
| AWDF | Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1â into the clear bits in DFSDM_FLTxAWCFR register). 0 (B_0x0): No Analog watchdog event occurred 1 (B_0x1): The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. |
| JCIP | Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1. 0 (B_0x0): No request to convert the injected channel group (neither by software nor by trigger) has been issued 1 (B_0x1): The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to '1â being written to JSWSTART or to a trigger detection |
| RCIP | Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1. 0 (B_0x0): No request to convert the regular channel has been issued 1 (B_0x1): The conversion of the regular channel is in progress or a request for a regular conversion is pending |
| CKABF | Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0) |
| SCDF | short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0) |