stm32 /stm32h7 /STM32H7B3 /DFSDM1 /DFSDM_FLT3RDATAR

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Interpret as DFSDM_FLT3RDATAR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATACH 0 (RPEND)RPEND 0RDATA

Fields

RDATACH

Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].

RPEND

Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion

RDATA

Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.

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