CLRROVRF=B_0x0, CLRJOVRF=B_0x0
| CLRJOVRF | Clear the injected conversion overrun flag 0 (B_0x0): Writing '0â has no effect 1 (B_0x1): Writing '1â clears the JOVRF bit in the DFSDM_FLTxISR register |
| CLRROVRF | Clear the regular conversion overrun flag 0 (B_0x0): Writing '0â has no effect 1 (B_0x1): Writing '1â clears the ROVRF bit in the DFSDM_FLTxISR register |
| CLRCKABF | Clear the clock absence flag CLRCKABF[y]=0: Writing '0â has no effect CLRCKABF[y]=1: Writing '1â to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0) |
| CLRSCDF | Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0â has no effect CLRSCDF[y]=1: Writing '1â to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0) |