RDMAEN=B_0x0, AWFSEL=B_0x0, JEXTEN=B_0x0, JDMAEN=B_0x0, JSCAN=B_0x0, JSYNC=B_0x0, FAST=B_0x0, JSWSTART=B_0x0, DFEN=B_0x0, RCH=B_0x0, RSYNC=B_0x0, RSWSTART=B_0x0, RCONT=B_0x0
| DFEN | DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state 0 (B_0x0): DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 1 (B_0x1): DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. |
| JSWSTART | Start a conversion of the injected group of channels This bit is always read as '0â. 0 (B_0x0): Writing '0â has no effect. 1 (B_0x1): Writing '1â makes a request to convert the channels in the injected conversion group, causing JCIP to become '1â at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing '1â has no effect if JSYNC=1. |
| JSYNC | Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 0 (B_0x0): Do not launch an injected conversion synchronously with DFSDM_FLT0 1 (B_0x1): Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger |
| JSCAN | Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel. 0 (B_0x0): One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 1 (B_0x1): The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. |
| JDMAEN | DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 0 (B_0x0): The DMA channel is not enabled to read injected data 1 (B_0x1): The DMA channel is enabled to read injected data |
| JEXTSEL | Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 … 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). |
| JEXTEN | Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 0 (B_0x0): Trigger detection is disabled 1 (B_0x1): Each rising edge on the selected trigger makes a request to launch an injected conversion 2 (B_0x2): Each falling edge on the selected trigger makes a request to launch an injected conversion 3 (B_0x3): Both rising edges and falling edges on the selected trigger make requests to launch injected conversions |
| RSWSTART | Software start of a conversion on the regular channel This bit is always read as '0â. 0 (B_0x0): Writing '0â has no effect 1 (B_0x1): Writing '1â makes a request to start a conversion on the regular channel and causes RCIP to become '1â. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1â has no effect if RSYNC=1. |
| RCONT | Continuous mode selection for regular conversions Writing '0â to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately. 0 (B_0x0): The regular channel is converted just once for each conversion request 1 (B_0x1): The regular channel is converted repeatedly after each conversion request |
| RSYNC | Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 0 (B_0x0): Do not launch a regular conversion synchronously with DFSDM_FLT0 1 (B_0x1): Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 |
| RDMAEN | DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). 0 (B_0x0): The DMA channel is not enabled to read regular data 1 (B_0x1): The DMA channel is enabled to read regular data |
| RCH | Regular channel selection … 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion). 0 (B_0x0): Channel 0 is selected as the regular channel 1 (B_0x1): Channel 1 is selected as the regular channel |
| FAST | Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN … for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN … for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (… but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input. 0 (B_0x0): Fast conversion mode disabled 1 (B_0x1): Fast conversion mode enabled |
| AWFSEL | Analog watchdog fast mode select 0 (B_0x0): Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 1 (B_0x1): Analog watchdog on channel transceivers value (after watchdog filter) |