stm32 /stm32h7 /STM32H7B3 /Flash /FLASH_CCR1

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Interpret as FLASH_CCR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLR_EOP1)CLR_EOP1 0 (CLR_WRPERR1)CLR_WRPERR1 0 (CLR_PGSERR1)CLR_PGSERR1 0 (CLR_STRBERR1)CLR_STRBERR1 0 (CLR_INCERR1)CLR_INCERR1 0 (CLR_RDPERR1)CLR_RDPERR1 0 (CLR_RDSERR1)CLR_RDSERR1 0 (CLR_SNECCERR1)CLR_SNECCERR1 0 (CLR_DBECCERR1)CLR_DBECCERR1 0 (CLR_CRCEND1)CLR_CRCEND1 0 (CLR_CRCRDERR1)CLR_CRCRDERR1

Fields

CLR_EOP1

Bank 1 EOP1 flag clear bit Setting this bit to 1 resets to 0 EOP1 flag in FLASH_SR1 register.

CLR_WRPERR1

Bank 1 WRPERR1 flag clear bit Setting this bit to 1 resets to 0 WRPERR1 flag in FLASH_SR1 register.

CLR_PGSERR1

Bank 1 PGSERR1 flag clear bit Setting this bit to 1 resets to 0 PGSERR1 flag in FLASH_SR1 register.

CLR_STRBERR1

Bank 1 STRBERR1 flag clear bit Setting this bit to 1 resets to 0 STRBERR1 flag in FLASH_SR1 register.

CLR_INCERR1

Bank 1 INCERR1 flag clear bit Setting this bit to 1 resets to 0 INCERR1 flag in FLASH_SR1 register.

CLR_RDPERR1

Bank 1 RDPERR1 flag clear bit Setting this bit to 1 resets to 0 RDPERR1 flag in FLASH_SR1 register.

CLR_RDSERR1

Bank 1 RDSERR1 flag clear bit Setting this bit to 1 resets to 0 RDSERR1 flag in FLASH_SR1 register.

CLR_SNECCERR1

Bank 1 SNECCERR1 flag clear bit Setting this bit to 1 resets to 0 SNECCERR1 flag in FLASH_SR1 register. If the DBECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well.

CLR_DBECCERR1

Bank 1 DBECCERR1 flag clear bit Setting this bit to 1 resets to 0 DBECCERR1 flag in FLASH_SR1 register. If the SNECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well.

CLR_CRCEND1

Bank 1 CRCEND1 flag clear bit Setting this bit to 1 resets to 0 CRCEND1 flag in FLASH_SR1 register.

CLR_CRCRDERR1

Bank 1 CRCRDERR1 flag clear bit Setting this bit to 1 resets to 0 CRCRDERR1 flag in FLASH_SR1 register.

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