PWR control register 1
| LPDS | Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit) |
| PVDE | Programmable voltage detector enable |
| PLS | Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. |
| DBP | Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. |
| FLPS | Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode. |
| BOOSTE | BOOSTE |
| AVD_READY | AVD_READY |
| SVOS | System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. |
| AVDEN | Peripheral voltage monitor on VDDA enable |
| ALS | Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. |
| AXIRAM1SO | AXIRAM1SO |
| AXIRAM2SO | AXIRAM2SO |
| AXIRAM3SO | AXIRAM3SO |
| AHBRAM1SO | AHBRAM1SO |
| AHBRAM2SO | AHBRAM2SO |
| ITCMSO | ITCMSO |
| GFXSO | GFXSO |
| HSITFSO | HSITFSO |
| SRDRAMSO | SRDRAMSO |