DMA1LPEN=B_0x0, USB1OTGLPEN=B_0x0, ADC12LPEN=B_0x0, CRCLPEN=B_0x0, DMA2LPEN=B_0x0, USB1ULPILPEN=B_0x0
| DMA1LPEN | DMA1 clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DMA1 clock disabled during CSleep mode 1 (B_0x1): DMA1 clock enabled during CSleep mode (default after reset) |
| DMA2LPEN | DMA2 clock enable during CSleep mode Set and reset by software. 0 (B_0x0): DMA2 clock disabled during CSleep mode 1 (B_0x1): DMA2 clock enabled during CSleep mode (default after reset) |
| ADC12LPEN | ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock. 0 (B_0x0): ADC1 and 2 peripheral clocks disabled during CSleep mode 1 (B_0x1): ADC1 and 2 peripheral clocks enabled during CSleep mode (default after reset) |
| CRCLPEN | CRC peripheral clock enable during CSleep mode Set and reset by software. 0 (B_0x0): CRC peripheral clock disabled during CSleep mode 1 (B_0x1): CRC peripheral clock enabled during CSleep mode (default after reset) |
| USB1OTGLPEN | USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock. 0 (B_0x0): USB1OTG peripheral clock disabled during CSleep mode 1 (B_0x1): USB1OTG peripheral clock enabled during CSleep mode (default after reset) |
| USB1ULPILPEN | USB_PHY1 clock enable during CSleep mode Set and reset by software. 0 (B_0x0): USB_PHY1 peripheral clock disabled during CSleep mode 1 (B_0x1): USB_PHY1 peripheral clock enabled during CSleep mode (default after reset) |