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stm32 /stm32h7 /STM32H7B3 /SPI1 /CFG1

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Interpret as CFG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSIZE0FTHVL0UDRCFG 0UDRDET 0 (RXDMAEN)RXDMAEN 0 (TXDMAEN)TXDMAEN 0CRCSIZE0 (CRCEN)CRCEN 0MBR

Description

configuration register 1

Fields

DSIZE

Number of bits in at single SPI data frame
FTHVL

threshold level
UDRCFG

Behavior of slave transmitter at underrun condition
UDRDET

Detection of underrun condition at slave transmitter
RXDMAEN

Rx DMA stream enable
TXDMAEN

Tx DMA stream enable
CRCSIZE

Length of CRC frame to be transacted and compared
CRCEN

Hardware CRC computation enable
MBR

Master baud rate

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32